1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more specifically, it relates to a semiconductor device which can improve element characteristics by a nitrogen implantation technique, and a method of fabricating the same.
2. Description of the Background Art
In general, it is known that source/drain regions of a MOS transistor are formed with shallow junction planes in order to suppress a short channel effect of the MOS transistor. In order to suppress a short channel effect of a P-channel MOS transistor (hereinafter referred to as "PMOS transistor"), it is effective to employ an electrode which is doped in a P type as an electrode material for the PMOS transistor. In order to suppress a short channel effect of an N-channel MOS transistor (hereinafter referred to as "NMOS transistor"), on the other hand, it is effective to employ an electrode which is doped in an N type as an electrode material for the NMOS transistor. A dual gate CMOS transistor is proposed in relation to application of these effects to a CMOS (complementary MOS) transistor which is formed by NMOS and PMOS transistors. In such a dual gate CMOS transistor, a gate electrode which is doped in an N type is employed for the NMOS transistor, while a gate electrode which is doped in a P type is employed for the PMOS transistor.
Conventional methods of forming source/drain regions of PMOS transistors with shallow junction planes are now described. FIG. 145 is a sectional view for illustrating a first conventional method of forming source/drain regions of a PMOS transistor with shallow junction planes, and FIGS. 146A and 146B are sectional views for illustrating a second method. Referring to FIG. 145, element isolation oxide film 7, a gate oxide film 2, a gate electrode 3, an oxide film 4 and side wall oxide films 5 are formed on a main surface of an N-type silicon substrate 1 through an ordinary process in the first method. Thereafter the element isolation oxide film 7, the oxide film 4 and the side wall oxide films 5 are employed as masks to ion-implant boron fluoride ions (BF.sub.2.sup.+) having a larger mass number than boron ions (B.sup.+) into the N-type silicon substrate 1. Thus, source/drain regions 6 are formed with shallow junction planes.
In the second method, element isolation oxide film 7, an oxide film 4 and side wall oxide films 5 are employed as masks to implant silicon ions (Si.sup.+) or germanium ions (Ge.sup.+) into an N-type silicon substrate 1, as shown in FIG. 146A. Thus, ion-implanted regions of the N-type silicon substrate 1 are brought into amorphous states. Thereafter boron ions (B.sup.+) are implanted into the N-type silicon substrate 1, as shown in FIG. 146B. Thus, source/drain regions 6 are formed with shallow junction planes. In the second method, the silicon ions or germanium ions are implanted in order to prevent a channeling phenomenon of the boron ions.
When the source/drain regions 6 are formed with shallow junction planes, however, the source/drain regions 6 are disadvantageously increased in sheet resistance. To this end, generally proposed is a countermeasure of providing titanium silicide films 8 having low resistance on surfaces of the source/drain regions 6, as shown in FIG. 147.
FIG. 148 is a sectional view showing an exemplary conventional dual gate CMOS transistor. Referring to FIG. 148, an N well 13 and a P well 14 are adjacently formed on a main surface of a P-type silicon substrate 11. Further, element isolation oxide film 12 are formed on the main surface of the P-type silicon substrate 11 at prescribed spaces. P-type source/drain regions 21 are formed on a main surface of the N well 13 at a prescribed space, to hold a channel region 10 therebetween. A gate electrode of a polycide gate structure formed by a polysilicon film 16 which is doped in a P type and a tungsten silicide film 18 which is formed on the polysilicon film 16 is provided on the channel region 10, through a gate oxide film 15. An oxide film 19 is formed on the tungsten silicide film 18. Side wall oxide films 20 are formed on side surfaces of the polysilicon film 16 and the tungsten silicide film 18.
On the other hand, N-type source/drain regions 22 are formed on a main surface of the P well 14 at a prescribed space, to hold a channel region 10 therebetween. A gate electrode of a polycide gate structure formed by a polysilicon film 17 which is doped in an N type and a tungsten silicide film 18 is provided on the channel region 10 in the P well 14, through a gate oxide film 15. An oxide film 19 is formed on the tungsten silicide film 18, while side wall oxide films 20 are formed on side surfaces of the polysilicon film 17 and the tungsten silicide film 18.
FIGS. 149 to 157 are sectional views for illustrating a fabrication process for the conventional dual gate CMOS transistor shown in FIG. 148. With reference to FIGS. 149 to 157, the fabrication process for the dual gate CMOS transistor shown in FIG. 148 is now described.
First, element isolation oxide film 12 are formed on a main surface of a P-type silicon substrate 11, as shown in FIG. 149. Further, an N well 13 serving as a PMOS transistor forming region and a P well 14 serving as an NMOS transistor forming region are formed on the main surface of the P-type silicon substrate 11, to be adjacent to each other.
Then, an oxide film 15a is formed to cover the N well 13 and the P well 14, as shown in FIG. 150. A polysilicon film 9 is formed on the oxide film 15a and the element isolation oxide film 12 by CVD, and a tungsten silicide film 18a is formed on the polysilicon film 9 by sputtering.
Then, the PMOS transistor forming region is covered with a resist film 25, as shown in FIG. 151. The resist film 25 is employed as a mask to implant arsenic ions (As.sup.+) into a portion of the polysilicon film 9 located on the NMOS transistor forming region. Thereafter the resist film 25 is removed.
Then, the NMOS transistor forming region is covered with a resist film 26 as shown in FIG. 152, and this resist film 26 is employed as a mask to implant boron fluoride ions (BF.sub.2.sup.+) into a portion of the polysilicon film 9 located on the PMOS transistor forming region. Thereafter the resist film 26 is removed. An oxide film is formed by CVD, and thereafter this oxide film, the tungsten silicide film 18a and the polysilicon film 9 are patterned in the form of gate electrodes by photolithography and anisotropic etching. Thus, the oxide films 19, the tungsten silicide films 18 and polysilicon films 16a and 17a are formed as shown in FIG. 153. Thereafter an oxide film is formed on the overall surface by CVD, and this oxide film is etched back. Thus, side wall oxide films 20 are formed on side surfaces of the gate electrodes, as shown in FIG. 154.
Then, the PMOS transistor forming region is covered with a resist film 27, as shown in FIG. 155. This resist film 27 is employed as a mask to implant arsenic ions into the NMOS transistor forming region. Thereafter the resist film 27 is removed.
Then, the NMOS transistor forming region is covered with a resist film 28 as shown in FIG. 156, and this resist film 28 is employed as a mask to implant boron fluoride ions into the PMOS transistor forming region. Thereafter the resist film 28 is removed. Heat treatment is carried out for activating the ions as implanted. Thus, a polysilicon film 16 which is doped in an N type, a polysilicon film 17 which is doped in a P type, N.sup.+ -type source/drain regions 22 and P.sup.+ -type source/drain regions 21 are formed as shown in FIG. 157. Thus, the exemplary conventional dual gate CMOS transistor of a polycide gate structure is completed.
FIG. 158 is a sectional view showing another exemplary conventional dual gate CMOS transistor. Referring to FIG. 158, titanium silicide films 23 are formed in a self-aligned manner on source/drain regions 21 and 22 and polysilicon films 16 and 17. Such a structure obtained by bringing surfaces of the polysilicon films 16 and 17 and the source/drain regions 21 and 22 for forming gate electrodes into silicide states in a self-aligned manner is called a salicide (self aligned silicide) structure. According to this salicide structure, it is possible to suppress increase of sheet resistance in the source/drain regions 21 and 22, which comes into question when the source/drain regions 21 and 22 are formed with shallow junction planes.
FIGS. 159 to 163 are sectional views for illustrating a fabrication process for the conventional dual gate CMOS transistor shown in FIG. 158. With reference to FIGS. 159 to 163, the fabrication process for the dual gate CMOS transistor shown in FIG. 158 is now described.
First, element isolation oxide film 12 are formed on a main surface of a P-type silicon substrate 11, as shown in FIG. 159. Further, an N well 13 and a P well 14 are formed on the main surface of the P-type silicon substrate 11 to be adjacent to each other. Oxide films 15a and polysilicon films (not shown) are successively formed on the N well 13 and the P well 14, and thereafter the polysilicon films are patterned to form patterned polysilicon films 8 as shown in FIG. 160.
Then, side wall oxide films 20 are formed on side surfaces of the polysilicon films 8, and thereafter a PMOS transistor forming region is covered with a resist film 25, as shown in FIG. 161. The resist film 25 is employed as a mask to ion-implant arsenic into the P well 14 and the polysilicon film 8 provided thereon. Thereafter the resist film 25 is removed.
Then, an NMOS transistor forming region is covered with a resist film 26, and this resist film 26 is employed as a mask to implant boron fluoride ions into the N well 13 and the polysilicon film 8 provided thereon, as shown in FIG. 162. Thereafter the resist film 26 is removed. A titanium layer (not shown) is formed on the overall surface by sputtering, and thereafter heat treatment is carried out to react silicon with titanium. Thus, titanium silicide films 23 are formed on source/drain regions 21 and 22 and polysilicon films 16 and 17, as shown in FIG. 163. Thus, the conventional dual gate CMOS transistor shown in FIG. 158 is completed.
As hereinabove described, the gate electrodes are brought into polycide gate structures of polysilicon films and tungsten silicide films, or brought into silicide states in the conventional dual gate CMOS transistor, in order to electrically connect the polysilicon film 16 which is doped in a P type with the polysilicon film 17 which is doped in an N type. In particular, it is possible to relieve the source/drain regions from increase of sheet resistance by employing a salicide structure for the dual gate CMOS transistor.
A thin film transistor (hereinafter referred to as "TFT") employing a polysilicon film is known as one of semiconductor devices. This TFT is an important device as a load transistor for a highly integrated SRAM or a driving transistor for a liquid crystal display. In relation to requirement for further improvement in integration and performance of an applied element of such a TFT, however, the TFT itself must be refined in structure and improved in electrical property as well as reliability.
Important subjects for refinement of the TFT are suppression of a short channel effect which is caused by impurity ions, forming source/drain regions, diffused into a channel region, and improvement of hot carrier resistance.
FIG. 164 is a sectional view showing a conventional PMOS-TFT. Referring to FIG. 164, an insulating film 102 is formed on a semiconductor substrate 101 in the conventional PMOS-TFT. A gate electrode 103 which is doped in a P type is formed on the insulating film 102. A gate insulating film 104 is formed to cover the gate electrode 103. A polysilicon layer 105 is formed on the gate insulating film 104. A P-type source region 105b and a P-type drain region 105c are formed in the polysilicon layer 105 at a prescribed space, to hold a channel region 105a therebetween. FIG. 165 is a perspective view showing an upper portion of the TFT shown in FIG. 164 including the gate electrode 103.
FIGS. 166 to 169 are sectional and perspective views for illustrating a fabrication process for the TFT shown in FIG. 164. With reference to FIGS. 166 to 169, the fabrication process for the conventional TFT is now described.
First, an insulating film 102 of a high temperature oxide film is formed on a semiconductor substrate 101 by CVD or the like, as shown in FIG. 166. A non-doped polysilicon layer 103a is formed on the insulating film 102 by CVD or the like. P-type impurity ions such as boron ions, for example, are ion-implanted into the non-doped polysilicon layer 103a. Thereafter a resist film 107 shown in FIG. 167 is formed on a prescribed region of the polysilicon layer 103a, and this resist film 107 is employed as a mask to anisotropically etch the polysilicon layer 103a (see FIG. 166). Thus, a gate electrode 103b is formed. Thereafter the resist film 107 is removed. A gate insulating film (not shown) is formed by thermal oxidation, and a non-doped polysilicon layer (not shown) is formed on the gate insulating film by CVD or the like. Thereafter arsenic ions for adjusting a threshold voltage are implanted into the non-doped polysilicon layer. A resist film (not shown) is formed on a prescribed region of the non-doped polysilicon layer, and thereafter the non-doped polysilicon layer and the gate insulating film are patterned. Thus, a gate insulating film 104 and a polysilicon layer 105 patterned as shown in FIG. 168 are formed. Thereafter the resist film is removed.
Then, a resist film 108 is formed on a region of the polysilicon layer 105 for forming a channel region. The resist film 108 is employed as a mask to ion-implant BF.sub.2.sup.+ into the polysilicon layer 105. Heat treatment is carried out for activating the impurity as implanted. Thus, a gate electrode 103, a source region 105b and a drain region 105c are formed. Thus, the conventional TFT shown in FIG. 164 is completed.
Another exemplary semiconductor device is a nonvolatile semiconductor memory device. In relation to such a nonvolatile semiconductor memory device, known is an EEPROM (electrically erasable and programmable read only memory) which can freely program data as well as electrically write and erase data. While this EEPROM can advantageously electrically write and erase data, it is difficult to highly integrate this memory since two transistors are required for a memory cell. To this end, there has been proposed a flash EEPROM having a memory cell formed by a single transistor, which can batch-erase written information charges. Such a flash EEPROM is disclosed in U.S. Pat. No. 4,868,619, for example.
FIG. 170 is a sectional view showing a conventional stack gate type flash EEPROM. Referring to FIG. 170, a drain region 208 and a source region 209 are formed on a main surface of a P-type silicon substrate 201 at a prescribed space, to hold a channel region 215 therebetween. A floating gate electrode 203 is formed on the channel region 215 through a thin oxide film 202 having a thickness of about 100 .ANG.. A control gate electrode 205 is formed on the floating gate electrode 203 through an interlayer insulating film 204. The floating gate electrode 203 and the control gate electrode 205 are formed by polysilicon layers. A thermal oxide film 216 is formed to cover the floating gate electrode 203, the control gate electrode 205 and the silicon substrate 201. A smooth coating film 212 of an oxide film or the like is formed on the thermal oxide film 216. Further, a wiring layer 214 of an aluminum alloy or the like is formed to cover the smooth coating film 212.
FIG. 171 is a schematic diagram for illustrating a conventional write operation of the flash EEPROM employing CHE (channel hot electrons). Referring to FIG. 171, a voltage V.sub.B1 of 6 to 8 V is applied to the drain region 208, and a voltage V.sub.G1 of 10 to 15 V is applied to the control electrode 205. Due to such application of the voltages V.sub.B1 and V.sub.G1, electrons having high energy are generated in the vicinity of the drain region 208 and the oxide film 202. Parts of the electrons are attracted to the gate electrode 203 by an electric field which is caused by the voltage V.sub.G1 applied to the control gate electrode 205, and injected into the floating gate electrode 203. When the electrons are thus stored in the floating gate electrode 203, a threshold voltage V.sub.TH of a control gate transistor exceeds a prescribed value. This state is a written state, which is called a state "0".
FIG. 172 is a schematic diagram for illustrating a conventional write operation of a flash EEPROM employing SHE (substrate hot electrons). With reference to FIG. 172, the write operation employing SHE is now described. In the flash EEPROM shown in FIG. 172, an N-channel control gate transistor is formed in a P well 222 which is provided on an N-type silicon substrate 221. In this case, a drain region 208 and a source region 209 are grounded, and a voltage V.sub.G2 of 10 to 15 V is applied to a control gate electrode 205. Further, a voltage V.sub.B2 of -5 to -10 V is applied to a substrate electrode 223. Due to such application of the voltages V.sub.G2 and V.sub.B2, a P-N junction which is formed by the N-type silicon substrate 221 and the P well 222 is biased in the forward direction. Thus, an ON-state current is generated. Parts of electrons forming the ON-state current are attracted to a floating gate electrode 203 by an electric field which is caused by the voltage V.sub.G2 applied to the control gate electrode 205, and injected into the floating gate electrode 203.
FIG. 173 is a schematic diagram for illustrating a write operation of a flash EEPROM employing an F-N (Fowler-Nordheim) tunnel phenomenon. With reference to FIG. 173, the write operation employing the F-N tunnel phenomenon is described. In F-N writing on a drain end, for example, a voltage V.sub.D3 of -10 to -12 V is applied to a drain region 208. Further, a control gate electrode 205 is held at a ground potential, and a source region 209 is maintained in a floating state. Due to an electric field caused by the voltage V.sub.D3 which is applied to the drain region 208, electrons pass through a thin oxide film 202 by an F-N tunnel phenomenon, to be injected into a floating gate electrode 203. Thus, the electrons are stored in the floating gate electrode 203, whereby a threshold voltage V.sub.TH of a control gate transistor is increased.
An erase operation is now described. A voltage V.sub.S of 10 to 12 V is applied to the source region 209, while the control gate electrode 205 is held at the ground potential and the drain region 208 is maintained in a floating state. Due to an electric field caused by the voltage V.sub.S which is applied to the source electrode 209, the electrons stored in the floating gate electrode 203 pass through the thin oxide film 202 by an F-N tunnel phenomenon. Thus, the electrons are extracted from the floating gate electrode 203, whereby the threshold voltage V.sub.TH of the control gate transistor is reduced. Data are erased when the threshold voltage V.sub.TH is reduced below a prescribed value. This state is called a state "1".
In read operation, further, a voltage V.sub.G4 of 5 V is applied to the control gate electrode 205 and a voltage V.sub.D4 of 1 to 2 V is applied to the drain region 208. Determination of the aforementioned state "0" or "1" is made depending on whether or not a current flows in a channel region of the control gate transistor, i.e., whether the control gate transistor is in an ON or OFF state. Thus, information is read out.
FIG. 174 is a model diagram for illustrating a coupling ratio of a conventional flash EEPROM. Referring to FIG. 174, the conventional flash EEPROM has a gate electrode of a two-layer structure, whereby a voltage which is applied to a control gate electrode 205 is applied to a channel region through a floating gate electrode 203. In other words, the potential of the floating gate electrode 203 is varied with the structures of an interlayer insulating film 204 and an oxide film 202, regardless of the amount of charges stored in the floating gate electrode 203 and values of potentials applied to respective terminals. A potential V.sub.FG of the floating gate electrode 203 depends on a threshold voltage V.sub.TH, a capacitance C.sub.FC between the floating gate electrode 203 and a control gate electrode 205, a capacitance C.sub.FB between the floating gate electrode 203 and a substrate 201, a capacitance C.sub.FS between the floating gate electrode 203 and a source region 209, and a capacitance C.sub.FD between the floating gate electrode 203 and a drain region 208, in addition to potentials applied to the respective terminals such as a control gate voltage V.sub.CG, a source voltage V.sub.S and a drain voltage V.sub.D. The potential V.sub.FG of the floating gate electrode 203 is approximately supplied by the following equation (1):
V.sub.FG =C.sub.FC V.sub.CG /C.sub.TOTAL +C.sub.FD V.sub.D /C.sub.TOTAL +(C.sub.FD +C.sub.FB)V.sub.S /C.sub.TOTAL +C.sub.FB V.sub.TH /C.sub.TOTAL +Q.sub.FG /C.sub.TOTAL (1) EQU Q.sub.FG =C.sub.FC (V.sub.FG -V.sub.CG)+C.sub.FD (V.sub.FG -V.sub.D)+C.sub.FS (V.sub.FG -V.sub.S)+C.sub.FB (V.sub.FG -V.sub.TH -V.sub.S)
where EQU C.sub.TOTAL =C.sub.FC +C.sub.FD +C.sub.FS +C.sub.FB
Referring to the above equation (1), the potential V.sub.CG of the control gate electrode 205 exerts an influence on the potential V.sub.FG of the floating gate electrode 203 in multiplication by C.sub.FC /C.sub.TOTAL, which is called a coupling ratio. When the coupling ratio is large, therefore, the potential V.sub.CG of the floating gate electrode 203 is increased regardless of the potential which is applied to the control gate electrode 205. Therefore, the transistor operation can be readily controlled by the potential which is applied to the control gate electrode 205, as the coupling ratio is increased.
When data are written and erased through F-N tunnel phenomenons in the aforementioned flash EEPROM, the oxide film 202 is broken in a certain probability, and hence element reliability is disadvantageously reduced. Due to tunneling of electrons through the oxide film 202, further, the electrons injected into the oxide film 202 are trapped therein in a certain probability. Thus, an interfacial level is formed in the interface between the silicon substrate 201 and the oxide film 202. Due to the interfacial level as formed, reliability of the oxide film 202 is so reduced that the threshold voltage is changed or current drivability is reduced as the result. Since a high potential is applied to the floating gate electrode 203, further, the source region 209 or the drain region 208 in data writing or erasing, a high electric field is caused in the interface between the drain region 208 or the source region 209 and the oxide film 202. In particular, adjacent memory cells share the drain region 208 in common, and hence a potential is applied also to the drain region 208 of a nonselected cell in data writing. Since the control gate electrode 205 of the nonselected cell is held at the ground potential, a high electric field is caused between the floating gate electrode 203 and the drain region 208. Interband tunneling is caused by the high electric field as shown in FIG. 175, leading to generation of electron-hole pairs. The holes as generated are injected into the oxide film 202 in a certain probability, resulting in an interfacial level which is caused in the interface between the silicon substrate 201 and the oxide film 202. Thus, the oxide film 202 is reduced in reliability.
In order to prevent such reduction in reliability of the oxide film 202, there has been proposed a method of suppressing generation of an interfacial level in the interface between the silicon substrate 201 and the oxide film 202. For example, there has been proposed a method of carrying out RTN (rapid thermal nitridation) treatment after formation of the oxide film 202, to introduce nitrogen into the oxide film 202. Since nitrogen terminates dangling bonds in the oxide film 202, whereby it is possible to prevent the oxide film 202 from trapping charges therein. The RTN treatment is adapted to carry out annealing for an extremely short time in a reactive gas atmosphere containing nitrogen such as ammonia (NH.sub.3), for example. Thus, nitrogen is incorporated into the silicon substrate 201 and the oxide film 202.
FIG. 176 is a sectional view showing a conventional buried channel type flash EEPROM. Referring to FIG. 176, an N-type impurity layer 217 is formed on a surface of a channel region 215, and a P-type impurity layer 218 is formed under the N-type impurity layer 217 in this buried channel type flash EEPROM. A buried channel layer is formed by the N-type and P-type impurity layers 217 and 218. In such a buried channel type flash EEPROM, no high electric field is applied across a source region 209 or a drain region 208 and an oxide film 202 dissimilarly to a surface channel type flash EEPROM, whereby it is possible to suppress occurrence of interband tunneling in this region. Therefore, it is possible to prevent generation of holes caused by interband tunneling in data writing or erasing, thereby preventing the oxide film 202 from injection of holes.
However, the conventional MOS transistors have the following problems:
In the conventional method of forming source/drain regions of a PMOS transistor shown in FIG. 145, boron fluoride ions having a large mass are implanted for forming the source/drain regions 6 with shallow junction planes. However, fluorine contained in the boron fluoride ions disadvantageously hinders reaction between titanium and silicon in formation of titanium silicide. Thus, excellent titanium silicide films cannot be formed on the surfaces of the source/drain regions 6 and the gate electrode 3.
In the conventional method of forming source/drain regions of a PMOS transistor shown in FIGS. 146A and 146B, the surface of the N-type silicon substrate 1 is brought into a preamorphous state by implantation of silicon ions or germanium ions, and hence high temperature heat treatment is required for crystal recovery. However, it is necessary to reduce the heat treatment in order to form the source/drain regions 6 with shallow junction planes, and hence crystal recovery is rendered insufficient, leading to increase of a junction leakage current. This problem is similarly caused also in formation of source/drain regions of an NMOS transistor.
In the conventional method of forming source/drain regions, further, it is difficult to form source/drain regions having shallow junction planes since impurities as implanted are diffused by heat treatment for activation in both of PMOS and NMOS transistors.
In the conventional NMOS and PMOS transistors, further, impurities doped in the gate electrodes are diffused in heat treatment steps to deteriorate the gate oxide films. Consequently, no sufficient hot carrier resistance can be attained upon progress of element refinement.
In each of the dual gate CMOS transistors shown in FIGS. 148 and 158, boron ions disadvantageously enter the channel region from the gate electrode of the PMOS transistor which is doped in a P type through the gate oxide film in the heat treatment step. Therefore, the threshold voltage of the transistor is disadvantageously changed. Particularly in the dual gate CMOS transistor of the polycide gate structure, arsenic ions and boron ions are mutually diffused in the silicide from the gate electrodes which are doped in N and P types respectively during the heat treatment step. Thus, work functions of the gate electrodes are varied, leading to fluctuation of the threshold voltages of the transistors.
In the conventional TFT shown in FIG. 164, on the other hand, the following problems are caused along progress of refinement. Namely, the impurity which is ion-implanted for forming the source/drain regions 105b and 105c is thermally diffused by the later heat treatment and disadvantageously diffused toward the channel region 105a. Thus, a punch-through phenomenon is caused to inhibit an original transistor operation. The punch-through phenomenon is such a phenomenon that a depletion layer in the vicinity of a drain is spread toward a source region when a channel length is small, and hence no current can be controlled by a gate voltage.
In the conventional TFT, further, hot carriers are generated when the electric field which is applied to the drain region 105c is increased in an OFF state, resulting in deterioration of element reliability.
On the other hand, the conventional flash EEPROM shown in FIG. 170 has the following problems: In general, RTN treatment is employed as a method of introducing nitrogen into the oxide film 202. However, the RTN treatment is generally adapted to carry out annealing in an ammonia atmosphere, and hence not only nitrogen but hydrogen is introduced into the oxide film 202, as shown in FIG. 177. The oxide film 202 is disadvantageously reduced in reliability due to such doping with hydrogen. Further, hydrogen and nitrogen are disadvantageously injected also into the silicon substrate 201 on the fabrication process.
In the RTN treatment, further, the silicon substrate 201 is exposed to a high temperature of about 1100.degree. C. while the treatment is carried out in a short time, and hence the peripheral temperature to which the silicon substrate 201 is exposed is abruptly changed. Thus, temperature distribution is caused in a prescribed plane of the silicon substrate 201, to cause slit-shaped defects due to difference in coefficient of expansion.
Further, the potential which is applied to the control gate electrode 205 is applied to the floating gate electrode 203 in multiplication by the coupling ratio. Therefore, it is necessary to apply the potential to the control gate electrode 205 in consideration of reduction by the coupling ratio. In order to apply a voltage of 5 V to the floating gate electrode 203 for writing data in a device having a coupling ratio of 0.5, for example, it is necessary to apply a voltage of about 10 V to the control gate electrode 205. Namely, the voltage which is applied to the control electrode 205 must be increased as the coupling ratio is reduced in order to guarantee a stable operation, and hence it is difficult to reduce the voltage of a power source for the flash EEPROM.
In general, there has been proposed a method of employing preparing the interlayer insulating film 204 from a nitride film having a higher dielectric constant than an oxide film, in order to improve the coupling ratio. When the interlayer insulating film 204 is formed only by a nitride film, however, a leakage current is disadvantageously increased. When the interlayer insulating film 204 is prepared from a composite film of a nitride film and an oxide film in order to prevent the problem of a leakage current, the interlayer insulating film 204 is disadvantageously increased in thickness. Thus, it is impossible to increase the coupling ratio.
In the conventional buried channel type flash EEPROM shown in FIG. 176, it is difficult to form a shallow buried channel layer by diffusion of an impurity which is implanted into the buried channel region. Thus, it is impossible to control the current between the source region 209 and the drain region 208 by the potential which is applied to the control gate electrode 205, and hence inconvenience such as a punch-through phenomenon is caused as the result.